NEWS & EVENTS
|
|
|
| |
 Semicon
Korea, Jan 29 - Feb 1, Seoul, Korea
SPIE
Microlithography 2008, Feb 24 - 29 San Jose, CA
IMAPS -
Device Packaging, Mar 17 - 20, Scottsdale, AZ
Surface
Preparation and Cleans, Mar 31- Apr 2, Austin, TX
Joint
sales and distribution agreement of Electronic Materials for 'Wafer
Level Packaging'
DynaloyTM
LLC Announces Advanced Thick Photoresist Remover
DynaloyTM LLC Welcomes Mr. Satoshi Kumasaka
Sign up to receive
the Dynaloy newsletter! |
|
|
TECH BULLETIN SPOTLIGHT
|
|
IDENTIFYING DEFECTS AND DETERMINING ROOT CAUSES FOUND DURING
THICK PHOTORESIST REMOVAL IN LEAD-FREE WLP
Two of the fastest growing segments of the integrated circuit
(IC) packing industry are FlipChip (FC) and Wafer Level
Packaging (WLP). The practice of incorporating FC or bump
technology in devices is experiencing significant growth. The
demand for WLPs is increasing due to their small form factor and
the increased demand for portable products. Batch packaging
offers cost reductions over packaging chips individually. Many
FCs produced through WLP end up in system-in-package
configurations, some are stacked while others are in planar
arrangements.
Current developments in WLPs include changing from leaded solder
to essentially field-unproven lead-free solders in order to be
compliant with the recently-introduced Restrictions of Hazardous
Substances (RoHS) directive. Advanced IC manufacturers and
packing sub-contractors are implementing lead-free
electroplating lines in their bumping facilities. Simplest
process integration schemes have involved directly replacing the
leaded solders with the lead-free equivalent while keeping all
the up-stream and down-stream process steps the same. With the
change in composition and plating parameters required by the
lead-free electroplating process, several process steps are
affected including, as examples, solder reflow which requires
higher temperatures and tighter ranges when compared with
eutectic solders, addition of new fluxes, and thick photoresist
removal after the electroplating step.
The focus of this paper is identifying defects that are found
during thick photoresist removal processes in lead-free wafer
level packaging and determining the root causes. The defect type
is metal residue after the field metal etch step. The metal
residue is found on the wafer surface, particularly in fine
pitch patterns and at the base of the solder bumps. Exploring
the root cause reveals a complex puzzle.
Read More...
(a)
(b)
Figure 1. SEM images showing the white ring
(a) 700 x, (b) 1800 x. The metal film propagates outward from the bump,
over the copper field metal.
|
|
|
|
