FlipChip (FC) and Wafer Level Packaging (WLP) are two of the fastest growing segments in the integrated circuit (IC) packaging industry. The practice of incorporating FC or bump technology in devices is experiencing significant growth, due to the improvement it provides in power and ground distribution, with the attendant reduction in simultaneous switching noise, (SSN). The demand for WLPs is increasing due to their small form factor and the increased demand for portable products.

Both FC and WLP technologies impose significant new demands related to the materials used for permanent dielectric layers and photoresists for fabrication processes. Cleaning chemistry must be designed to remove highly cross-linked films such as photoresists and fluxes; but keep the solder bump, exposed metals, under-bump metallization (UBM), and dielectrics undamaged. Device reliability and performance rely heavily on the proper working of all these components. In situ or discrete analytical procedures are required for testing the reliability of the materials used.

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Wafer level packaging (WLP) encompasses a large number of processes including
FlipChip processes for printed and plated and ball drop bumps. Most recently various 3-D
processes, including through silicon via (TSV) processes and modified ShellOP processes
are being refined. Each is characterized by many steps that have their own technical
challenges. Today, one of the ‘most prevalent and most critical of all semiconductor
manufacturing process steps is wafer cleaning. […] it has evolved to the point where not
only most cleans must be specifically tailored to the preceding or subsequent fabrication
steps, but to a level of sophistication that is better labeled as surface preparation or surface
engineering.

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Wafer level packaging (WLP) encompasses a large number of processes including
FlipChip processes for printed and plated and ball drop bumps. Most recently various 3-D
processes, including through silicon via (TSV) processes and modified ShellOP processes
are being refined. Each is characterized by many steps that have their own technical
challenges. Today, one of the ‘most prevalent and most critical of all semiconductor
manufacturing process steps is wafer cleaning. […] it has evolved to the point where not
only most cleans must be specifically tailored to the preceding or subsequent fabrication
steps, but to a level of sophistication that is better labeled as surface preparation or surface
engineering.

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Due to the economic downturn and rising costs of raw materials and finished goods, many
industries are exploring strategies to improve processes while simultaneously reducing costs. In
the semiconductor industry, such measures are being taken to reduce the cost of photoresist
removal. To accomplish this goal, Dynastrip™ DL88™ was formulated and optimized as a
cleaning solution suited for positive photoresist removal in both thin and thick film applications.
These applications include cleaning processes in wafer bumping, bond pad formation, and
sensitive metal line formation. Dynastrip DL88 meets the criteria of complete polymer removal
from the surface and removes resists such as AZ 1513, AZ 10xt, and Shipley 827(Dow Chemical
Company). The solution also meets low metal etch rate criteria on copper, aluminum, titanium,
and leaded and lead-free solders. It is compatible with polyimide, silicon, and SiOx, and does not
attack permanent materials on the wafer surface. In addition to meeting the above criteria,
Dynastrip DL88 was formulated in keeping with Dynaloy’s commitment to be a responsible
steward of the environment by providing green technology. This poster describes the polymer
removal characteristics of Dynastrip DL88 and the removal processes which together, meet the
desired goal of cost of ownership reduction.

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